The connection machine
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Computer networks
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
A framework for adaptive routing in multicomputer networks
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Proceedings of the fifth MIT conference on Advanced research in VLSI
Tight bounds for oblivious routing in the hypercube
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Adaptive, minimal routing in hypercubes
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Methods for message routing in parallel machines
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Requirements for deadlock-free, adaptive packet routing
PODC '92 Proceedings of the eleventh annual ACM symposium on Principles of distributed computing
The DASH prototype: implementation and performance
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
The design of the Caltech Mosaic C multicomputer
Proceedings of the 1993 symposium on Research on integrated systems
The J-machine multicomputer: an architectural evaluation
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
An efficient algorithm for gray-to-binary permutation on hypercubes
Journal of Parallel and Distributed Computing
The turn model for adaptive routing
Journal of the ACM (JACM)
Adaptive Deadlock- and Livelock-Free Routing in the Hypercube Network
IEEE Transactions on Parallel and Distributed Systems
Adaptive Deadlock- and Livelock-Free Routing with All Minimal Paths in Torus Networks
IEEE Transactions on Parallel and Distributed Systems
Storage-Efficient, Deadlock-Free Packet Routing Algorithms for Torus Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
On the Conversion Between Binary Code and Binary-Reflected Gray Code on Binary Cubes
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The chaos router chip: design and implementation of an adaptive router
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
ROMM Routing: A Class of Efficient Minimal Routing Algorithms
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Performance Evaluation of Adaptive Routing Algorithms for k-ary-n-cubes
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Universal schemes for parallel communication
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
A Critique of Adaptive Routing
A Critique of Adaptive Routing
THE MIT ALEWIFE MACHINE: A LARGE-SCALE DISTRIBUTED-MEMORY MULTIPROCESSOR
THE MIT ALEWIFE MACHINE: A LARGE-SCALE DISTRIBUTED-MEMORY MULTIPROCESSOR
An information dispersal approach to issues in parallel processing
An information dispersal approach to issues in parallel processing
Worst-case traffic for oblivious routing functions
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Locality-preserving randomized oblivious routing on torus networks
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Matrix Transpose on Meshes: Theory and Practice
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Throughput-centric routing algorithm design
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Increasing the throughput of an adaptive router in network-on-chip (NoC)
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Static virtual channel allocation in oblivious routing
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Path-based, randomized, oblivious, minimal routing
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
Locality-preserving randomized multicast routing on k-ary n-cube
ICOIN'09 Proceedings of the 23rd international conference on Information Networking
rHALB: a new load-balanced routing algorithm for k-ary n-cube networks
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Design of a router for network-on-chip
International Journal of High Performance Systems Architecture
Weighted random oblivious routing on torus networks
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A novel 3D layer-multiplexed on-chip network
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
On-Chip Network Evaluation Framework
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Throughput-Effective On-Chip Networks for Manycore Accelerators
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
Microprocessors & Microsystems
Analysis of application-aware on-chip routing under traffic uncertainty
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms
Microprocessors & Microsystems
Randomized partially-minimal routing: near-optimal oblivious routing for 3-D mesh networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing on-chip networks for throughput accelerators
ACM Transactions on Architecture and Code Optimization (TACO)
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