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Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
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ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
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Proceedings of the 38th annual Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
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Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
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ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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Proceedings of the 2003 international symposium on Low power electronics and design
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Proceedings of the conference on Design, automation and test in Europe - Volume 3
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Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
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ICCD '04 Proceedings of the IEEE International Conference on Computer Design
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Proceedings of the 32nd annual international symposium on Computer Architecture
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
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ITNG '07 Proceedings of the International Conference on Information Technology
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ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
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Journal of Systems Architecture: the EUROMICRO Journal
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip
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Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
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Computers and Electrical Engineering
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstraction. Experimental results show that our power macro model incurs less than 5% average absolute cycle error compared to gate level analysis. The high level power macro model allows network power to be readily incorporated into simulation infrastructures, providing a fast and cycle accurate power profile, to enable power optimization such as power-aware compiler, core mapping, and scheduling techniques for CMP. As a case study, we demonstrate the use of our model for evaluating the effect of different core mappings using SPLASH-2 benchmark showing the utility of our power macro model.