Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Space-time scheduling of instruction-level parallelism on a raw machine
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Compiler Support for Scalable and Efficient Memory Systems
IEEE Transactions on Computers
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing
IEEE Transactions on Parallel and Distributed Systems
Microarchitectural exploration with Liberty
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Energy characterization of a tiled architecture processor with on-chip networks
Proceedings of the 2003 international symposium on Low power electronics and design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Discovering and Exploiting Program Phases
IEEE Micro
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Exploiting last idle periods of links for network power management
Proceedings of the 5th ACM international conference on Embedded software
Compiler-directed proactive power management for networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Compiler-directed voltage scaling on communication links for reducing power consumption
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reducing NoC energy consumption through compiler-directed channel voltage scaling
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Achieving structural and composable modeling of complex systems
International Journal of Parallel Programming - Special issue: The next generation software program
High-level power analysis for multi-core chips
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
The case for low-power photonic networks on chip
Proceedings of the 44th annual Design Automation Conference
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage-saving opportunities in mesh-based massive multi-core architectures
ACM SIGARCH Computer Architecture News
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
An analytical approach for network-on-chip performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
TransCom: transforming stream communication for load balance and efficiency in networks-on-chip
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A modular simulator framework for network-on-chip based manycore chips using UNISIM
Transactions on High-Performance Embedded Architectures and Compilers IV
The optimum network on chip architectures for video object plane decoder design
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
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As on-chip networks become prevalent in multiprocessor systems-on-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power increasingly the primary constraint in chips, the tool chain in systems design, from simulation infrastructures to compilers and synthesis frameworks, needs to take network power into account, motivating the need for early-stage communication power analysis.While there has been substantial research in network performance analysis that enabled critical insights into network design, no power analysis frameworks for networks exist. In this paper, we propose such a framework that takes as input message flows, and derives a power profile of the network fabric, capturing both the spatial variance across the network fabric as well as the temporal variance across application execution time. Our analysis is based on link utilization as the unit of abstraction for network power, with contention among message flows modeled through propagation of overflow areas in link utilization functions. When validated against Orion, a cycle-accurate network power simulator, we show that relative trends in network power are well-preserved. We then demonstrate potential uses of our analysis framework through three case studies, from speedup of multiprocessor and network simulations, to facilitating power-aware communication synthesis and compiler code placement.