Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
The Computer Journal
A trade-off between space and efficiency for routing tables
Journal of the ACM (JACM)
SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Neural networks: a systematic introduction
Neural networks: a systematic introduction
Pulsed neural networks
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A multi-sender asynchronous extension to the AER protocol
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Mesh Distance Formulae
Networks on chip
High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Towards cortex sized artificial neural systems
Neural Networks
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Connection-centric network for spiking neural networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Which model to use for cortical spiking neurons?
IEEE Transactions on Neural Networks
A hierachical configuration system for a massively parallel neural hardware platform
Proceedings of the 9th conference on Computing Frontiers
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
Neural Processing Letters
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Providing highly flexible connectivity is a major architectural challenge for hardware implementation of reconfigurable neural networks. We perform an analytical evaluation and comparison of different configurable interconnect architectures (mesh NoC, tree, shared bus and point-to-point) emulating variants of two neural network topologies (having full and random configurable connectivity). We derive analytical expressions and asymptotic limits for performance (in terms of bandwidth) and cost (in terms of area and power) of the interconnect architectures considering three communication methods (unicast, multicast and broadcast). It is shown that multicast mesh NoC provides the highest performance/cost ratio and consequently it is the most suitable interconnect architecture for configurable neural network implementation. Routing table size requirements and their impact on scalability were analyzed. Modular hierarchical architecture based on multicast mesh NoC is proposed to allow large scale neural networks emulation. Simulation results successfully validate the analytical models and the asymptotic behavior of the network as a function of its size.