1994 Special Issue: Design and evolution of modular neural network architectures
Neural Networks - Special issue: models of neurodynamics and behavior
Networks of spiking neurons: the third generation of neural network models
Transactions of the Society for Computer Simulation International - Special issue: simulation methodology in transportation systems
Neural Networks: A Comprehensive Foundation
Neural Networks: A Comprehensive Foundation
Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Modular Neural Network Task Decomposition Via Entropic Clustering
ISDA '06 Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications - Volume 01
Evolving neural networks for fractured domains
Proceedings of the 10th annual conference on Genetic and evolutionary computation
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Connection-centric network for spiking neural networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors
ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
Hardware spiking neural network prototyping and application
Genetic Programming and Evolvable Machines
A novel approach for the implementation of large scale spiking neural networks on FPGA hardware
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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Biologically-inspired packet switched network on chip (NoC) based hardware spiking neural network (SNN) architectures have been proposed as an embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in SNNs require large distributed on-chip memory, which poses serious challenges for compact hardware implementation of such architectures. Based on the structured neural organisation observed in human brain, a modular neural networks (MNN) design strategy partitions complex application tasks into smaller subtasks executing on distinct neural network modules, and integrates intermediate outputs in higher level functions. This paper proposes a hardware modular neural tile (MNT) architecture that reduces the SNN topology memory requirement of NoC-based hardware SNNs by using a combination of fixed and configurable synaptic connections. The proposed MNT contains a 16:16 fully-connected feed-forward SNN structure and integrates in a mesh topology NoC communication infrastructure. The SNN topology memory requirement is 50 % of the monolithic NoC-based hardware SNN implementation. The paper also presents a lookup table based SNN topology memory allocation technique, which further increases the memory utilisation efficiency. Overall the area requirement of the architecture is reduced by an average of 66 % for practical SNN application topologies. The paper presents micro-architecture details of the proposed MNT and digital neuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65 nm low-power CMOS technology. The evolvable capability of the proposed MNT and its suitability for executing subtasks within a MNN execution architecture is demonstrated by successfully evolving benchmark SNN application tasks representing classification and non-linear control functions. The paper addresses hardware modular SNN design and implementation challenges and contributes to the development of a compact hardware modular SNN architecture suitable for embedded applications