A novel approach for the implementation of large scale spiking neural networks on FPGA hardware

Authors:
B. Glackin;T. M. McGinnity;L. P. Maguire;Q. X. Wu;A. Belatreche
Affiliations:
Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, UK
Venue:
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Year:
2005

Citing 9
Cited 10

The implementation of fuzzy systems, neural networks and fuzzy neural networks using

Information Sciences: an International Journal
Neural Networks: A Comprehensive Foundation

Neural Networks: A Comprehensive Foundation
Spiking Neuron Models: An Introduction

Spiking Neuron Models: An Introduction
Hardware Requirements for Spike-Processing Neural Networks

IWANN '96 Proceedings of the International Workshop on Artificial Neural Networks: From Natural to Artificial Neural Computation
Hardware spiking neural network with run-time reconfigurable connectivity in

EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
Intrinsic and extrinsic implementation of a bio-inspired hardware system

Information Sciences—Informatics and Computer Science: An International Journal - Special issue: Bio-inspired systems (BIS)
Biophysics of Computation: Information Processing in Single Neurons (Computational Neuroscience Series)

Biophysics of Computation: Information Processing in Single Neurons (Computational Neuroscience Series)
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems

Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
Post-synaptic Time-dependent Conductances in Spiking Neurons: FPGA Implementation of a Flexible Cell Model

IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods

Challenges for large-scale implementations of spiking neural networks on FPGAs

Neurocomputing
2008 Special Issue: Compact hardware liquid state machines on FPGA for real-time speech recognition

Neural Networks
Processing visual stimuli using hierarchical spiking neural networks

Neurocomputing
A Hardware Accelerated Simulation Environment for Spiking Neural Networks

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks

International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system

Proceedings of the 7th ACM international conference on Computing frontiers
Experimental demonstration of associative memory with memristive neural networks

Neural Networks
PAX: A mixed hardware/software simulation platform for spiking neural networks

Neural Networks
Hardware spiking neural network prototyping and application

Genetic Programming and Evolvable Machines
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network

Neural Processing Letters

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a strategy for the implementation of large scale spiking neural network topologies on FPGA devices based on the I&F conductance model. Analysis of the logic requirements demonstrate that large scale implementations are not viable if a fully parallel implementation strategy is utilised. Thus the paper presents an alternative approach where a trade off in terms of speed/area is made and time multiplexing of the neuron model implemented on the FPGA is used to generate large network topologies. FPGA implementation results demonstrate a performance increase over a PC based simulation.