The Handbook of Brain Theory and Neural Networks
The Handbook of Brain Theory and Neural Networks
A Mixed-Mode Analog Neural Network Using Current-Steering Synapses
Analog Integrated Circuits and Signal Processing
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
A gradient descent rule for spiking neurons emitting multiple spikes
Information Processing Letters - Special issue on applications of spiking neural networks
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A silicon synapse based on a charge transfer device for spiking neural network application
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
A novel approach for the implementation of large scale spiking neural networks on FPGA hardware
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
A neuromorphic VLSI device for implementing 2D selective attention systems
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Neural network implementation using a single MOST per synapse
IEEE Transactions on Neural Networks
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Adaptive routing strategies for large scale spiking neural network hardware implementations
ICANN'11 Proceedings of the 21th international conference on Artificial neural networks - Volume Part I
Hardware spiking neural network prototyping and application
Genetic Programming and Evolvable Machines
Outline of a general theory of behavior and brain coordination
Neural Networks
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
Neural Processing Letters
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FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE), incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.