Neural network implementation using a single MOST per synapse

Authors:
D. E. Johnson;J. S. Marsland;W. Eccleston
Affiliations:
Dept. of Electr. Eng. & Electron., Liverpool Univ.;-;-
Venue:
IEEE Transactions on Neural Networks
Year:
1995

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Abstract

A VLSI implementation of an artificial neural network using a single n-channel MOS (metal-oxide semiconductor) transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and by using a novel technique to manipulate negative weights. A simple multilayer perceptron (MLP) network was simulated using the SPICE circuit simulator and the performance of a hardware realization of the same MLP network was measured. Simulations and measurements are shown to agree well