EMBRACE: emulating biologically-inspired architectures on hardware
NN'08 Proceedings of the 9th WSEAS International Conference on Neural Networks
Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a new approach in realizing Virtual Channels tailored for Network on Chip implementations. The technique makes use of a flow control mechanism based on adaptive input rate control where the required buffer size is independent of the number of channels and the packet size. The resulting implementation requires only 3% of the memory space used in a conventional implementation of virtual channels. The efficient use of memory storage does also deliver performance improvements that can be up to 15% for a normal network configuration.