Wireless interconnects for clock distribution
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Global interconnect design in a three-dimensional system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multimedia Applications of Multiprocessor Systems-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A silicon synapse based on a charge transfer device for spiking neural network application
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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This paper highlights and discusses the current challenges in the implementation of large scale Spiking Neural Networks (SNNs) in hardware. A mixed-mode approach to realising scalable SNNs on a reconfigurable hardware platform is presented. The approach uses compact low power analogue spiking neuron cells, with a weight storage capability, interconnected using Network on Chip (NoC) routers. Results presented show that this route to hardware implementation is promising.