Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Field-programmable gate arrays
Field-programmable gate arrays
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Universal switch-module design for symmetric-array-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Hierarchical interconnection structures for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Compact, multilayer layout for butterfly fat-tree
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Routing Architectures for Hierarchical Field Programmable Gate Arrays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Proceedings of the 45th annual Design Automation Conference
EMBRACE: emulating biologically-inspired architectures on hardware
NN'08 Proceedings of the 9th WSEAS International Conference on Neural Networks
Energy and switch area optimizations for FPGA global routing architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel routing architecture for field-programmable gate-arrays
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
Hardware spiking neural network prototyping and application
Genetic Programming and Evolvable Machines
Interlaced switch boxes placement for three-dimensional FPGA architecture design
International Journal of Circuit Theory and Applications
Location, location, location: the role of spatial locality in asymptotic energy minimization
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's mesh-of-trees (MoT), which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge" arity-4 MoT networks require 26% fewer switches than the standard, Manhattan FPGA routing scheme.