Performances improvement of FPGA using novel multilevel hierarchical interconnection structure

Authors:
Hayder Mrabet;Zied Marrakchi;Pierre Souillot;Habib Mehrez
Affiliations:
Université Pierre et Marie Curie, Paris, France;Université Pierre et Marie Curie, Paris, France;Université Pierre et Marie Curie, Paris, France;Université Pierre et Marie Curie, Paris, France
Venue:
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Year:
2006

Citing 11
Cited 2

Fat-trees: universal networks for hardware-efficient supercomputing

IEEE Transactions on Computers
PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Hierarchical interconnection structures for field programmable gate arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A generic architecture for on-chip packet-switched interconnections

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
Routing Architectures for Hierarchical Field Programmable Gate Arrays

ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Design of FPGA interconnect for multilevel metallization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unifying mesh- and tree-based programmable interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new Multilevel Hierarchical MFPGA and its suitable configuration tools

ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Efficient tree topology for FPGA interconnect network

Proceedings of the 18th ACM Great Lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in traditional topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results based on the MCNC benchmarks show that MFPGA can implement circuits with an average gain of 40% in total area compared with mesh architecture.