Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Introduction to parallel algorithms and architectures: array, trees, hypercubes
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Field-programmable gate arrays
Field-programmable gate arrays
The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay
IEEE Transactions on Computers
Area-speed tradeoffs for hierarchical field-programmable gate arrays
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Rent's rule based switching requirements
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FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Track placement: orchestrating routing structures to maximize routability
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IEEE Design & Test
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ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IBM Journal of Research and Development - POWER5 and packaging
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 2008 international workshop on System level interconnect prediction
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Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
The Journal of Supercomputing
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We examine the traditional, symmetric, Manhattan mesh design for field-programmable gate-array (FPGA) routing along with tree-of-meshes (ToM) and mesh-of-trees (MoT) based designs. All three networks can provide general routing for limited bisection designs (Rent's Rule with p c,p) MoT design can be mapped to a (2c,p) linear population ToM and introduce a corner turn scheme which will make it possible to perform the reverse mapping from any (2c,p) linear population ToM to a (2c,p) MoT augmented with a particular set of corner turn switches. One consequence of this latter mapping is a multilayer layout strategy for N-node, linear population ToM designs that requires only Θ(N) two-dimensional area for any p when given sufficient wiring layers. We further show upper and lower bounds for global mesh routes based on recursive bisection width and show these are within a constant factor of each other and within a constant factor of MoT and ToM layout area. In the process we identify the parameters and characteristics which make the networks different, making it clear there is a unified design continuum in which these networks are simply particular regions.