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IEEE Transactions on Computers
VLSI theory and parallel supercomputing
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
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AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
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SODA '91 Proceedings of the second annual ACM-SIAM symposium on Discrete algorithms
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Packet routing in networks with long wires
Area-universal interconnection networks for VLSI parallel computers
Area-universal interconnection networks for VLSI parallel computers
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Journal of Algorithms
Fast Algorithms for Manipulating Formal Power Series
Journal of the ACM (JACM)
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
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IEEE Transactions on Parallel and Distributed Systems
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ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
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ACM '78 Proceedings of the 1978 annual conference
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FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Generic Universal Switch Blocks
IEEE Transactions on Computers
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Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
Area-Universal Circuits with Constant Slowdown
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
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Proceedings of the 2003 ACM symposium on Applied computing
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A segmented parallel-prefix VLSI circuit with small delays for small segments
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
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Journal of Parallel and Distributed Computing - Special issue: 18th International parallel and distributed processing symposium
Area-time tradeoffs for universal VLSI circuits
Theoretical Computer Science
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This paper shows that a fat-pyramid of area /spl Theta/(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more untenable as the size of parallel systems increases. This paper concentrates on simulation using transmission lines (wires along which bits can be pipelined) with the message routing schedule set up off line, but it also discusses the extension to on-line simulation. This paper also examines the capabilities of a fat-pyramid when matched against a substantially larger network and points out the surprising difficulty of doing such a comparison without the unit wire delay assumption.