A segmented parallel-prefix VLSI circuit with small delays for small segments

Authors:
Bradley C. Kuszmaul
Affiliations:
MIT CSAIL, Cambridge, Massachusetts
Venue:
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
Year:
2005

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Abstract

I present a VLSI circuit for segmented parallel prefix with gate delay O(log S) and wire delay.