Communications of the ACM
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
An evaluation of asynchronous addition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A CMOS VLSI Implementation of an Asynchronous ALU
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Practical Design and Performance Evaluation of Completion Detection Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Synthesis of high-performance self-checking delay-insensitive tree circuits
Synthesis of high-performance self-checking delay-insensitive tree circuits
A formal approach to designing delay-insensitive circuits
Distributed Computing
The logic of computer arithmetic
The logic of computer arithmetic
A segmented parallel-prefix VLSI circuit with small delays for small segments
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
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Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the logic complexity is a linear function of $n$, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of $n$. To the best of our knowledge, our adder has the best area-time efficiency which is $\Theta(n\log\log n)$. An economic implementation of this adder in CMOS technology is also presented. SPICE simulation results show that, based on random inputs, our 32-bit self-timed carry-lookahead adder is 2.39 and 1.42 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively; and, based on statistical data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively.