Design of a high-speed square root multiply and divide unit
IEEE Transactions on Computers
Discovering auxiliary information for incremental computation
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Self-Timed Carry-Lookahead Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
The pyramid teaching computer structures by computer structures
ACM SIGCSE Bulletin
Hardware Efficient Algorithms for Trigonometric Functions
IEEE Transactions on Computers
Computer architecture courses in electrical engineering departments
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Addition in signed digit number systems
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
Computer architecture in U. S. and Canadian electrical engineering departments
SIGCSE '74 Proceedings of the fourth SIGCSE technical symposium on Computer science education
The emergence of computational arithmetic as a component of the computer science curriculum
SIGCSE '70 Proceedings of the first SIGCSE technical symposium on Education in computer science
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Novel Implementation Method for Addition and Subtraction in Residue Number Systems
IEEE Transactions on Computers
Binary Multiplication with Overlapped Addition Cycles
IEEE Transactions on Computers
Multiple Operand Addition and Multiplication
IEEE Transactions on Computers
An Augmented Iterative Array for High-Speed Binary Division
IEEE Transactions on Computers
Sign Detection in Residue Number Systems
IEEE Transactions on Computers
Tree Realizations of Iterative Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
A Minimum Table Size Result for Higher Radix Nonrestoring Division
IEEE Transactions on Computers
The ILLIAC IV Processing Element
IEEE Transactions on Computers
Cellular Logic Array for High-Speed Signed Binary Number Multiplication
IEEE Transactions on Computers
Multiplication Using Logarithms Implemented with Read-Only Memory
IEEE Transactions on Computers
Binary Logic for Residue Arithmetic Using Magnitude Index
IEEE Transactions on Computers
Conditional-Sum Early Completion Adder Logic
IEEE Transactions on Computers
Synthesis and Comparison of Two's Complement Parallel Multipliers
IEEE Transactions on Computers
Distribution of Runs in Binary Words
IEEE Transactions on Computers
On Translation Algorithms in Residue Number Systems
IEEE Transactions on Computers
Some Comments on Postcorrections for Nonrestoring Division
IEEE Transactions on Computers
A bounded carry inspection adder for fast parallel arithmetic
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Fast multiplication cellular arrays for LSI implementation
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
An interactive simulator generating system for small computers
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
Multiple operand addition and multiplication
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
A Note on Conditional-Sum Addition for Base - 2 Systems
IEEE Transactions on Computers
Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication
IEEE Transactions on Computers
Concurrent error detection for group look-ahead binary adders
IBM Journal of Research and Development
High-speed multiplication systems
IEEE Transactions on Computers
A 33MHz 16-bit gradient calculator for real-time volume imaging
EGGH'94 Proceedings of the Ninth Eurographics conference on Graphics Hardware
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