The logic of computer arithmetic
The logic of computer arithmetic
IEEE Transactions on Computers
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
Journal of Systems Architecture: the EUROMICRO Journal
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 14.98 |
A method for designing the read-only memories (ROM's) needed for multiplication using logarithms is developed. By defining the word length of the multiplicand, multiplier, and product as n bits and the word length of -the rounded logarithms as m bits, design curves are given that allow various values of n and m to be selected for a given multiplier accuracy. Then a table is used to determine, which combination results in an implementation with the least number of bits.