ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Sign/Logarithm Arithmetic for FFT Implementation
IEEE Transactions on Computers
A Piecewise Linear Approximation of Log2x with Equal Maximum Errors in All Intervals
IEEE Transactions on Computers
Multiplication Using Logarithms Implemented with Read-Only Memory
IEEE Transactions on Computers
A Real-Time Hardware System for Digital Processing of Wide-Band Video Images
IEEE Transactions on Computers
IEEE Transactions on Computers
The Sign/Logarithm Number System
IEEE Transactions on Computers
FPGA-based System for Real-Time Video Texture Analysis
Journal of Signal Processing Systems
A register transfer module FFT processor for speech analysis
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Journal of Signal Processing Systems
An iterative logarithmic multiplier
Microprocessors & Microsystems
Design of a high precision logarithmic converter in a binary floating point divider
Concurrency and Computation: Practice & Experience
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An approximate method for rapid multiplication or division with relatively simple digital circuitry is described. The algorithm consists of computing approximate binary logarithms, adding or subtracting the logarithms, and computing the approximate anti- logarithm of the resultant. Using a criteria of minimum mean square error, coefficients for the approximations are developed. An error analysis is given for three cases in which the algorithm is useful. Finally, applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.