Computer Arithmetic
IEEE Transactions on Computers
The Sign/Logarithm Number System
IEEE Transactions on Computers
Comments on "Sign/Logarithm Arithmetic for FFT Implementation"
IEEE Transactions on Computers
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
IEEE Transactions on Computers
A Novel Cotransformation for LNS Subtraction
Journal of Signal Processing Systems
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sign/logarithm arithmetic is applicable to a variety of numerical applications where wide dynamic range and small wordsize are required. In this paper the basic sign/logarithm arithmetic operations required for signal processing (i.e., addition, subtraction, and multiplication) are reviewed, the computational errors are analyzed for FFT realization, and simulation results are presented which serve to verify the analysis. It is shown that the sign/logarithm approach provides improved arithmetic quantization error performance for a given word size over FFT's implemented with conventional fixed or floating point arithmetic, and that the sign/logarithm implementation is faster and less complex than conventional approaches.