An Algorithm for the Computation of Binary Logarithms
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Approximating Elementary Functions with Symmetric Bipartite Tables
IEEE Transactions on Computers
Arithmetic on the European Logarithmic Microprocessor
IEEE Transactions on Computers - Special issue on computer arithmetic
Error Analysis of the Kmetz/Maenner Algorithm
Journal of VLSI Signal Processing Systems
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Low-Power Properties of the Logarithmic Number System
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
A Single-Multiplier Quadratic Interpolator for LNS Arithmetic
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
VLSI Implementation of a Low-Power Antilogarithmic Converter
IEEE Transactions on Computers
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
A Scalable Architecture for LDPC Decoding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation
IEEE Transactions on Computers
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation
Journal of VLSI Signal Processing Systems
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Multiplication Using Logarithms Implemented with Read-Only Memory
IEEE Transactions on Computers
Decoder design for RS-based LDPC codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Flexible LDPC decoder design for multigigabit-per-second applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient decoder design for nonbinary quasicyclic LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
Journal of Systems Architecture: the EUROMICRO Journal
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
A nonbinary LDPC decoder architecture with adaptive message control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of massively parallel hardware multi-processors for highly-demanding embedded applications
Microprocessors & Microsystems
An approximate logarithmic squaring circuit with error compensation for DSP applications
Microelectronics Journal
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Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC) design (in 0.18- µm CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations.