Low-Power Properties of the Logarithmic Number System
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
VLSI Implementation of a Low-Power Antilogarithmic Converter
IEEE Transactions on Computers
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
High-accuracy fixed-width modified booth multipliers for lossy applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A simple pipelined squaring circuit for DSP
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
A Low Complexity Euclidean Norm Approximation
IEEE Transactions on Signal Processing
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
Low Cost Hardware Implementation of Logarithm Approximation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The squaring function is one of the frequently used arithmetic functions in DSP, so an approximation of the squaring function is acceptable as long as this approximation corrupts the bits that are already corrupted by noise, and does not degrade application@?s performance significantly. Approximation of the squaring function can lead to significant savings in hardware and processing time. Previously proposed approximations of the squaring function include LUT-based solutions, linear interpolation of the squaring function and minimization of combinational logic. This paper proposes approximation based on a simple logarithmic interpolation of a squaring function with a simple logic block, which can be reused for the error compensation. The proposed block performs approximation of the squaring function with a shift operation and a carry-free subtraction. The proposed approximate squarer with one compensation block achieves the average relative error below 1.5% for any bit length, while maintaining a low power consumption. In order to evaluate the device utilization, the propagation delay and power consumption and to compare it with the existing solutions, we have synthesized the proposed squarer and the existing solutions for the standard cell library and 0.25@mm CMOS process parameters.