Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: Linear interpolation requires a single multiplication but is significantly less accurate than quadratic interpolation. The latter requires two multiplications. Two novel quadratic interpolation schemes are shown here that approximate the functions required by the Logarithmic Number System (LNS) with more accuracy than linear interpolation using only a single multiplication. One method uses two ROMs to give the accuracy of quadratic interpolation, whilst the other uses one ROM to give four- to six-bits better accuracy than linear interpolation. These techniques save four- to eight-fold on memory compared to linear interpolation for the same accuracy. We illustrate the usefulness of these techniques for serial implementation with a clone of the ARM TM microprocessor (known as AWE) that we developed to have LNS instructions. We also show a novel technique for decreasing the propagation delay in both linear and quadratic interpolation that stores the logarithm of the derivative of the function in a ROM, rather than the function itself.