On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Very High Radix Square Root with Prescaling and Rounding and a Combined Division/Square Root Unit
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
Very-High Radix CORDIC Rotation Based on Selection by Rounding
Journal of VLSI Signal Processing Systems - special issue on CORDIC
A subroutine method for calculating logarithms
Communications of the ACM
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
On-the-Fly Rounding (Computing Arithmetic)
IEEE Transactions on Computers
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
IEEE Transactions on Computers
Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root
IEEE Transactions on Computers
High-Radix Logarithm with Selection by Rounding
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Reviewing 4-to-2 Adders for Multi-Operand Addition
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Reduced Power Consumption for MPEG Decoding with LNS
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Symmetric Bipartite Tables for Accurate Function Approximation
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ICCD '98 Proceedings of the International Conference on Computer Design
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Software Manual for the Elementary Functions (Prentice-Hall series in computational mathematics)
Software Manual for the Elementary Functions (Prentice-Hall series in computational mathematics)
High-speed algorithms and architectures for range reduction computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A high-radix digit-recurrence algorithm for the computation of the logarithm, and an analysis of the tradeoffs between area and speed for its implementation, are presented in this paper. Selection by rounding is used in iterations j 驴 2, and by table look-up in the first iteration. A sequential architecture is proposed, and estimates of the execution time and hardware requirements are obtained for n = 16, 24, 32, 53 and 64 bits of precision and for radix values from r = 8 to r = 1024. These estimates are obtained according to an approximate model for the delay and area of the main logic blocks. We show that the most efficient implementations are obtained for radices ranging from r = 32 to r = 256, reducing the execution time by half with respect to a radix-4 implementation with redundant arithmetic.