High-speed algorithms and architectures for range reduction computation

Authors:
Francisco J. Jaime;Miguel A. Sánchez;Javier Hormigo;Julio Villalba;Emilio L. Zapata
Affiliations:
Computers Architecture Department, Málaga University, Málaga, Spain;Computers Architecture Department, Málaga University, Málaga, Spain;Computers Architecture Department, Málaga University, Málaga, Spain;Computers Architecture Department, Málaga University, Málaga, Spain;Computers Architecture Department, Málaga University, Málaga, Spain
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

Citing 5
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Abstract

Range reduction is a crucial step for accuracy in trigonometric functions evaluation. This paper shows and compares a set of algorithms for additive range reduction computation and their corresponding application-specific integrated circuit implementations (ensuring an accuracy of one unit in the last place). A word-serial architecture implementation has been used as a reference for clearer comparisons. Besides, a new tablebased pipelined architecture for range reduction has also been proposed.