Pipelined Architecture for Additive Range Reduction

Authors:
Francisco J. Jaime;Julio Villalba;Javier Hormigo;Emilio L. Zapata
Affiliations:
Department of Computers Architecture, University of Málaga, Escuela Técnica Superior de Ingeniería Informática, Campus de Teatinos, Málaga, Spain 29017;Department of Computers Architecture, University of Málaga, Escuela Técnica Superior de Ingeniería Informática, Campus de Teatinos, Málaga, Spain 29017;Department of Computers Architecture, University of Málaga, Escuela Técnica Superior de Ingeniería Informática, Campus de Teatinos, Málaga, Spain 29017;Department of Computers Architecture, University of Málaga, Escuela Técnica Superior de Ingeniería Informática, Campus de Teatinos, Málaga, Spain 29017
Venue:
Journal of Signal Processing Systems
Year:
2008

Citing 6
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Abstract

Range reduction is a crucial step for the accuracy in trigonometric functions evaluation. A new pipelined architecture to deal with range reduction for floating point representation is presented in this paper. The algorithm is based on a look-up table storing the corresponding powers of 2 mod A. The overall design has been optimized for a modulo equal to 2驴, which is the most widely used due to trigonometric functions requirements. We provide an evaluation of different configurations and a full error propagation study which ensures an accuracy of one unit in the last place.