Acceleration of Series
Implementing complex elementary functions using exception handling
ACM Transactions on Mathematical Software (TOMS)
Toward Correctly Rounded Transcendentals
IEEE Transactions on Computers
Floating Point Verification in HOL Light: The Exponential Function
Formal Methods in System Design
Journal of VLSI Signal Processing Systems
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
IEEE Transactions on Computers
A Continued-Fraction Analysis Of Trigonometric Argument Reduction
IEEE Transactions on Computers
A New Range-Reduction Algorithm
IEEE Transactions on Computers
Degree reduction for trigonometric functions
ACM SIGNUM Newsletter
Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations
IEEE Transactions on Computers
Pipelined Architecture for Additive Range Reduction
Journal of Signal Processing Systems
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An accurate reduction poses little difficulty for arguments of a few radians. However for, say, a CRAY1, H format on the VAX, or double extended in the proposed IEEE standard, the maximum argument which might be presented for reduction is of the order of 2^16000 radians. Accurate reduction of such an argument would require storage of π (or its reciprocal) to over 16,000 bits. Direct reduction by division (or multiplication) then requires generation of a somewhat larger number of bits in the result in order to guarantee the accuracy of the reduction. Of these bits only the low few bits of the integer part of the quotient (product) and enough bits to correctly round the remainder are relevant; the rest will be discarded.