A low error and high performance multiplexer-based truncated multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal processing. The Mitchell Algorithm (MA) proposed in [9], is a simple and low cost approach commonly used for logarithmic multiplication. However, the method involves high error due to piecewise straight line approximation of the logarithm curve. Several methods have been proposed in the literature for improving the accuracy of Mitchell's Algorithm. In this paper, we propose a new method for improving the accuracy of MA using Operand Decomposition (OD). The OD process decreases the number of bits with the value of '1' in the multiplicands and reduces the amount of approximation. The proposed method decreases the error percentage of the Mitchell Algorithm by 44.7% on the average. Since the proposed method does not require any correction term it can be used in combination with other methods for improving the accuracy of the MA based multiplier. Experimental results are presented for random input data, signal and image processing applications, which clearly indicate that the proposed method significantly outperforms previous methods proposed in the literature.