Pseudorandom Rounding for Truncated Multipliers
IEEE Transactions on Computers
Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications
IEEE Transactions on Computers
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
Data Compression: The Complete Reference
Data Compression: The Complete Reference
Reduced Power Dissipation Through Truncated Multiplication
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Design of low-error fixed-width modified booth multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
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This paper proposes a novel adaptive pseudo-carry compensation truncation (PCT) scheme, which is derived for the multiplexer based array multiplier. The proposed method yields low average error among existing truncation methods. The new PCT based truncated array multiplier outperforms other existing truncated array multipliers by as much as 25% in terms of silicon area and delay, and consumes about 40% less dynamic power than the full-width multiplier for 32-bit operation. The proposed truncation scheme is applied to an image compression algorithm. Due to its low truncation error, the mean square errors (MSE) of various reconstructed images are found to be comparable to those obtained with full-precision multiplication.