Design of low-error fixed-width modified booth multiplier

Authors:
Kyung-Ju Cho;Kwang-Chul Lee;Jin-Gyun Chung;Keshab K. Parhi
Affiliations:
Department of Electronic and Information Engineering, and Information and Communication Research Institute, Chonbuk National University, Chonju 561-756, Korea;Samsung Thales Company, Yongin 449-712, Korea.;Department of Electronic and Information Engineering, and Information and Communication Research Institute, Chonbuk National University, Chonju 561-756, Korea;Broadcom Corporation, Irvine, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 35% reduction in area and power consumption of a multiplier compared with the ideal multiplier.