Design of low-error fixed-width modified booth multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Radix rkFFTs: matricial representation and SDC/SDF pipeline implementation
IEEE Transactions on Signal Processing
A 2.4-GS/s FFT processor for OFDM-based WPAN applications
IEEE Transactions on Circuits and Systems II: Express Briefs
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This paper presents a high-speed low-complexity modified radix - 25 512-point fast Fourier transform (FFT) processor using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix - 25 FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twiddle factor memory. It also uses a complex constant multiplier instead of a complex Booth multiplier. The proposed FFT processor achieves a signal-to-quantization noise ratio of 35 dB at 12 bit internal word length. The proposed processor has been designed and implemented using 90-nm CMOS technology with a supply voltage of 1.2 V. The results demonstrate that the total gate count of the proposed FFT processor is 290 K. Furthermore, the highest throughput rate is up to 2.5 GS/s at 310 MHz while requiring much less hardware complexity.