Error control systems for digital communication and storage
Error control systems for digital communication and storage
Design of low-error fixed-width modified booth multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic IP generation of FFT/IFFT processors with word-length optimization for MIMO-OFDM systems
EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
A high-speed low-complexity modified radix - 25 FFT processor for high rate WPAN applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18-μm CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity and low power consumption.