Fixed-Width Multiplier for DSP Application

Authors:
Hui-Hsuan Wang
Affiliations:
-
Venue:
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

Citing 2
Cited 3

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Design of low-error fixed-width modified booth multiplier

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Low-error and hardware-efficient fixed-width multiplier by using the dual-group minor input correction vector to lower input correction vector compensation error

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Abstract

A new compensation method that reduces the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based on compensation method are carried out on array multiplier and booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.