Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
Fixed-Width Multiplier for DSP Application
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Design of low-error fixed-width modified booth multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
Journal of VLSI Signal Processing Systems
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
IEEE Transactions on Circuits and Systems for Video Technology
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An efficient implementation for the computation of the forward quantization of H.264/AVC is presented. It uses a modified reformulation of quantization expressions, in full compliance with the standard, combined with an adaptive truncated Booth multiplier to reduce hardware complexity. The JM reference software's C code has been rewritten to analyze the effect of the proposed approach. Simulations carried out on several typical video sequences with different texture characteristics demonstrate the validity of this approach with an improvement in the PSNR at low QP, between a maximum of +0.8 dB and a minimum of 0.3 dB, with a slight increment in the bit-rate of about 0.8 %. However, this improvement is smoothed for typical values of QP and only an insignificant difference is found with respect to the JM results. The proposed architecture synthesized in the AMS 0.35μm technology, which is suitable for VLSI implementation, reduces the area by 26 %, the power by 32 % and the critical path delay by 21 % in comparison with a classic implementation.