Introduction to data compression (2nd ed.)
Introduction to data compression (2nd ed.)
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
Proceedings of the International Conference on Advances in Computing, Communication and Control
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
Journal of Signal Processing Systems
Optimized Hardware Implementation for Forward Quantization of H.264/AVC
Journal of Signal Processing Systems
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H.264/AVC also known as MPEG 4 part 10 or JVT, is a recently established video coding standard by the Joint Video Team (JVT) of the ISO/IEC MPEG and ITU-T VCEG. The main goal of the paper is to give a broader understanding of the design considerations for the transform and quantization blocks from H.264/AVC, by presenting area and speed optimized implementations of these blocks. The area optimized design can be used in low performance applications like mobile devices, while the speed optimized designs can be used in high definition encoders. Various designs with these blocks were synthesized with 0.18 μm TSCM technology and were also implemented on a Xilinx FPGA. The resulting gate counts were anywhere from 294 to 47,762 gates and the throughput was anywhere from 6 to 2,552 M pixels/s depending on block and optimization. In addition, a system on a programmable chip implementation of the DCT and quantization blocks is presented, which uses the Xilinx Virtex II-Pro's FPGA and its Power PC. Using this system it is possible to process 0.8 M pixels/s.