Introduction to data compression (2nd ed.)
Introduction to data compression (2nd ed.)
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
Journal of VLSI Signal Processing Systems
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
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With continuous advancement of VLSI technology it has become possible to achieve any desired performance metric, but at a cost of increased system complexity. In this paper we present area optimal integer 2-D DCT architecture for H.264/AVC codecs. The 2-D DCT calculation is performed by utilizing the separability property, in such a way, 2-D DCT is divided into two 1-D DCT calculation that share a common memory, which considerably reduces the gate count. Due to its area optimized approach the design will find application in hand-held/mobile devices. The transform module has been coded in Verilog hardware description language (HDL) and synthesized in 0.18μ TSMC technology.