A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
Journal of VLSI Signal Processing Systems
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Journal of Signal Processing Systems
ASIP-controlled Inverse Integer Transform for H.264/AVC Compression
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
Combined CAVLC decoder, inverse quantizer, and transform kernel in compact H.264/AVC decoder
IEEE Transactions on Circuits and Systems for Video Technology
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Design and Implementation of Integer Transform and Quantization Processor for H.264 Encoder on FPGA
ACT '09 Proceedings of the 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents an ASIC processor chip for real-time implementation of the computing of the complete process of forward transform, quantization, inverse transform, dequantization, and reconstruction of a 16驴脳驴16 macroblock in full compliance with the H.264/AVC video coding standard. This processor is capable of processing 4驴脳驴4 blocks without interruption, with a parallelism in the data-path of 16 data/cycle, in a pipeline architecture with the twofold aim of achieving high operation frequency and high throughput. To implement the four 4驴脳驴4 transforms and two 2驴脳驴2 transforms required in the H.264/AVC coding system, two configurable multitransform direct 2-D architectures are used, one for forward and another for inverse. Moreover, a reduction in hardware is achieved by reformulating of quantization and dequantization equations and appropriately adjusting the datapath bus widths. A prototype of this processor chip was fabricated in the HCMOS9 STMicroelectronics 130 nm standard cell technology. The latency for 16驴脳驴16 macroblocks is 26 clock cycles in normal mode and 42 in Intra 16驴脳驴16 mode with a maximum operating frequency of 280 MHz and a throughput of 4,480 Mpixels/s. As a result, our processor chip is able to support the UHDTV 7680驴脳驴4320@60 Hz (3 G sample/s) format requirement.