A low-cost very large scale integration architecture for multistandard inverse transform
IEEE Transactions on Circuits and Systems II: Express Briefs
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
Journal of Signal Processing Systems
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In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4x4 and 8x8 inverse integer transform with additional support for 2x2 and 4x4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4x4 circuit in the 8x8 circuit, while achieving a speed of 176MHz.