IEEE Transactions on Computers
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Journal of Signal Processing Systems
ASIP-controlled Inverse Integer Transform for H.264/AVC Compression
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
Fast algorithm and low-cost hardware-sharing design of multiple integer transforms for VC-1
IEEE Transactions on Circuits and Systems II: Express Briefs
Low cost design of a hybrid architecture of integer inverse DCT for H.264, VC-1, AVS, and HEVC
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Efficient hardware implementation of 8 × 8 integer cosine transforms for multiple video codecs
Journal of Real-Time Image Processing
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In this brief, a low-cost very large scale integration (VLSI) architecture is designed for multistandard inverse transform. The proposed architecture is used in multistandard decoder of MPEG-2, MPEG-4 ASP, H.264/AVC and VC-1. Two circuit share strategies, factor share (FS) and adder share (AS), are applied to the inverse transform architecture for saving its circuit resource. It is shown that the proposed multistandard inverse transform architecture can support the real-time decoding of 1920 × 1080@60 Hz high-definition video at the cost of low circuit resource.