Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse
IEEE Transactions on Circuits and Systems for Video Technology
A low-cost very large scale integration architecture for multistandard inverse transform
IEEE Transactions on Circuits and Systems II: Express Briefs
A dual quad-tree based variable block-size coding method
Journal of Visual Communication and Image Representation
Configurable, low-power design for inverse integer transform in H.264/AVC
Proceedings of the 8th International Conference on Frontiers of Information Technology
A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC
Image Communication
Low cost design of a hybrid architecture of integer inverse DCT for H.264, VC-1, AVS, and HEVC
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
Journal of Signal Processing Systems
Efficient hardware implementation of 8 × 8 integer cosine transforms for multiple video codecs
Journal of Real-Time Image Processing
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In H.264/AVC, the concept of adapting the transform size to the block size of motion-compensated prediction residue has proven to be an important coding tool. This paper presents highly parallel joint circuit architecture for 8驴脳驴8 and 4驴脳驴4 adaptive block-size transforms in H.264/AVC. By decomposing the 8驴脳驴8 transform to basic 4驴脳驴4 transforms, a unified architecture is designed for both 8驴脳驴8 and 4驴脳驴4 transform and the transform data-path can be efficiently reused for six kinds of transforms. i.e., 8驴脳驴8 forward, 8驴脳驴8 inverse, 4驴脳驴4 forward, 4驴脳驴4 inverse, forward-Hadamard, inverse-Hadamard transforms. Linear shift mapping is applied on the memory buffer to support parallel access both in row and column directions which eliminates the need for a transpose circuit. For reusable and configurable transform data-path, a multiple-stage pipeline is designed to reduce the critical path length and increase throughput. The design is implemented under UMC 0.18 um technology at 200 MHz with 13.651 K logic gates, which can support 1,920驴脳驴1,088 30 fps H.264/AVC HDTV decoder.