A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Journal of Signal Processing Systems
A Multitransform Architecture for H.264/AVC High-Profile Coders
IEEE Transactions on Multimedia
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264
IEEE Transactions on Circuits and Systems for Video Technology
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The inverse integer transform is one of the compute-intensive processing units in an H.264/AVC video decoder. In this paper, we propose a configurable, low-power design for the inverse integer transform in an H.264/AVC decoder for video processing applications running on battery-powered electronic devices such as mobile phone. The proposed design is based on a data-driven computation algorithm for the inverse integer transform. It efficiently exploits the zero-valued coefficients in the input blocks to reduce dynamic power consumption. The area-requirement for the hardware implementation of the proposed design is reduced by designing configurable processing units to share the same hardware resources on the device. The proposed design is described in VHDL and is synthesized under 0.18μm CMOS standard cell technology. The experimental results show that the proposed design consumes significantly less dynamic power (up to 80% reduction) when compared with existing conventional design for the inverse integer transform, with a small area-overhead (approximately 2K gates).