High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip
Journal of VLSI Signal Processing Systems
A processor-in-memory architecture for multimedia compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shift-register-based data transposition for cost-effective discrete cosine transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Journal of Signal Processing Systems
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
A novel fast DCT coefficient scan architecture
PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
IEEE Transactions on Circuits and Systems for Video Technology
A novel linear array for discrete cosine transform
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
A novel linear array for discrete cosine transform
WSEAS Transactions on Circuits and Systems
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
A low complexity multiplierless transform coding for HEVC
PCM'12 Proceedings of the 13th Pacific-Rim conference on Advances in Multimedia Information Processing
On reconfiguration-oriented approximate adder design and its application
Proceedings of the International Conference on Computer-Aided Design
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This paper first reviewed the two-dimensional discrete cosine transform (2-D DCT) and inverse DCT (IDCT) architectures. Then a new VLSI architecture, namely the transpose free row column decomposition method (TF-RCDM), for 2-D DCT/IDCT is proposed. The new RCDM architecture replaces the transpose circuits with permutation networks and parallel memory modules. As results, the timing overhead of I/O operations is eliminated and the hardware complexity is largely reduced. An accuracy testing system is designed to find the optimum word-length parameters. Based on the accuracy testing system, the proposed architecture has achieved the smallest word-length among the reported 2-D DCT architectures. Synthesis results showed that with 0.25-μm CMOS technology library, the area was about 1.5 mm2 and the speed was about 125 MHz.