Expanding the Range of Convergence of the CORDIC Algorithm
IEEE Transactions on Computers
A Storage Efficient Way to Implement the Discrete Cosine Transform
IEEE Transactions on Computers
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
An efficient CORDIC array structure for the implementation ofdiscrete cosine transform
IEEE Transactions on Signal Processing
A cost-effective 8×8 2-D IDCT core processor with folded architecture
IEEE Transactions on Consumer Electronics
Low-power multiplierless DCT architecture using image correlation
IEEE Transactions on Consumer Electronics
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
IEEE Transactions on Circuits and Systems for Video Technology
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
IEEE Transactions on Circuits and Systems for Video Technology
A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array
IEEE Transactions on Circuits and Systems for Video Technology
New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse
IEEE Transactions on Circuits and Systems for Video Technology
A new time distributed DCT architecture for MPEG-4 hardware reference model
IEEE Transactions on Circuits and Systems for Video Technology
New systolic array implementation of the 2-D discrete cosine transform and its inverse
IEEE Transactions on Circuits and Systems for Video Technology
Memory-efficient and high-performance 2-D DCT and IDCT processors based on CORDIC rotation
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms
Proceedings of the 24th symposium on Integrated circuits and systems design
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Two-dimensional discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8×8 DCT and IDCT processors. In which, only one bank of SRAM (64 words) and coefficient ROM (6 words) is utilized for saving the memory space. The kernel arithmetic unit, i.e. multiplier, which is demanding in the implementation of DCT and IDCT processors, has been replaced by simple adders and shifters based on the double rotation CORDIC algorithm. The proposed architectures for 2-D DCT and IDCT processors not only simplify hardware but also reduce the power consumption with high performances.