An Efficient IDCT Processor Design for HDTV Applications
Journal of VLSI Signal Processing Systems
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip
Journal of VLSI Signal Processing Systems
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems
Journal of Signal Processing Systems
Error-resistance and Low-complexity Integer Inverse Discrete Cosine Transform
Journal of Signal Processing Systems
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
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A dedicated cost-effective core processor of the 8×8 two-dimensional (2-D) inverse discrete transform (IDCT) architecture based on the direct realization approach is proposed. The folding scheme is developed to obtain a low gate-count and high throughput. The experimental result shows that the chip's throughput is one pixel per clock cycle with a structure of 78 K transistors, which reveals that the low cost of VLSI implementation is more attractive than most of previously reported chips. With 0.6 μm CMOS, double metal technology, the chip is a standard-cell implementation and requires a core size of 4.4×2.8 mm2, and is able to operate at a clock rate of more than 100 MHz