Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
A Parallel Accelerator Architecture for Multimedia Video Compression
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
High Performance Array Processor for Video Decoding
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Memory-efficient and high-performance 2-D DCT and IDCT processors based on CORDIC rotation
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel image processing with the block data parallel architecture
IBM Journal of Research and Development
High throughput DA-based DCT with high accuracy error-compensated adder tree
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
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A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N2 multipliers to evaluate N×N-point DCTs at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required