A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms

Authors:
Hyesook Lim;Vincenzo Piuri;Earl E. Swartzlander
Affiliations:
Lucent Technologies, Cisco Systems, San Jose, California;Politecnico di Milano, Milano, Italy;Univ. of Texas, Austin, Texas
Venue:
IEEE Transactions on Computers
Year:
2000

Citing 9
Cited 7

VLSI array processors

VLSI array processors
Discrete-time signal processing

Discrete-time signal processing
Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition

IEEE Transactions on Computers
Multidimensional Fourier transforms by systolic architectures

Journal of VLSI Signal Processing Systems
A VLSI architecture for the real time computation of discrete trigonometric transforms

Journal of VLSI Signal Processing Systems - Application specific array processors
Systolic Signal Processing Systems

Systolic Signal Processing Systems
Multidimensional systolic arrays and their implementations for discrete fourier transform and discrete cosine transform

Multidimensional systolic arrays and their implementations for discrete fourier transform and discrete cosine transform
Unified systolic arrays for computation of the DCT/DST/DHT

IEEE Transactions on Circuits and Systems for Video Technology
New systolic array implementation of the 2-D discrete cosine transform and its inverse

IEEE Transactions on Circuits and Systems for Video Technology

Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
New Characterizations of 2D Discrete Cosine Transform

IEEE Transactions on Computers
Discrete cosine and sine transforms: regular algorithms and pipeline architectures

Signal Processing
Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

Computers and Electrical Engineering
An FPGA-based fault-tolerant 2D systolic array for matrix multiplications

Transactions on computational science XIII
Software-Oriented system-level simulation for design space exploration of reconfigurable architectures

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
2-D discrete cosine transform (DCT) on meshes with hierarchical control modes

IbPRIA'05 Proceedings of the Second Iberian conference on Pattern Recognition and Image Analysis - Volume Part I

Quantified Score

Hi-index	14.98

Visualization

Abstract

The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.