Systolic Signal Processing Systems

A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms

IEEE Transactions on Computers

A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications

IEEE Transactions on Computers

A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms

IEEE Transactions on Parallel and Distributed Systems

On the effect of spare positioning on the reconfigurability of two-dimensional processor arrays

PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis

Matrix Manipulations Using Artificial Neural Networks

Journal of Integrated Design & Process Science

Rigid molecule docking: FPGA reconfiguration for alternative force laws

EURASIP Journal on Applied Signal Processing