Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication
IEEE Transactions on Computers
Systolic Signal Processing Systems
Systolic Signal Processing Systems
| Hi-index | 14.98 |
In this work, the design of a Galois enhanced quadratic residue number system (GEQRNS) [9], [7] processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been optimized to perform multiply-accumulate type operations on complex operands. The properties of finite fields have been exploited to perform this complex multiplication in a manner which results in greatly reduced hardware complexity. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which can occur during operation. The combination of these two factors makes this an ideal candidate for array signal processing applications, where high complex arithmetic data rates are required. A prototype processing element has been fabricated in 1.5 驴m CMOS technology, which is shown to operate at 40 MHz.