An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems
IEEE Transactions on Computers
On Modulus Replication for Residue Arithmetic Computations of Complex Inner Products
IEEE Transactions on Computers
New Multipliers Modulo 2/sup N/-1
IEEE Transactions on Computers - Special issue on computer arithmetic
New Fault Tolerant Techniques for Residue Number Systems
IEEE Transactions on Computers
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings
IEEE Transactions on Computers
Signed-Digit Architecture for Residue to Binary Transformation
IEEE Transactions on Computers
Design of a High-Speed Square Generator
IEEE Transactions on Computers
A Fast Modified CORDIC—Implementation of Radial Basis Neural Networks
Journal of VLSI Signal Processing Systems
A Look-Up Scheme for Scaling in the RNS
IEEE Transactions on Computers
Finding smooth integers in short intervals using CRT decoding
STOC '00 Proceedings of the thirty-second annual ACM symposium on Theory of computing
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
A high performance RNS multiply-accumulate unit
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Multi-voltage low power convolvers using the polynomial residue number system
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Journal of VLSI Signal Processing Systems
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
Performance Studies of a Reside Number System Based CDMA System over Bursty Communication Channels
Wireless Personal Communications: An International Journal
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Large Dynamic Range Computations Over Small Finite Rings
IEEE Transactions on Computers
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications
IEEE Transactions on Computers
Implementing Multiplication with Split Read-Only Memory
IEEE Transactions on Computers
A Number System with Continuous Valued Digits and Modulo Arithmetic
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
Journal of VLSI Signal Processing Systems
Finding smooth integers in short intervals using CRT decoding
Journal of Computer and System Sciences - Special issue on STOC 2000
New power-of-2 RNS scaling scheme for cell-based IC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Residue number system to binary converter for the moduli set (2n-1, 2n - 1, 2n + 1)
Journal of Systems Architecture: the EUROMICRO Journal
An arithmetic residue to binary conversion technique
Integration, the VLSI Journal
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Wireless Personal Communications: An International Journal
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Complex ±1 Multiplier Based on Signed-Binary Transformations
Journal of VLSI Signal Processing Systems
Large Systems of Boolean Functions: Realization by Modular Arithmetic Methods
Automation and Remote Control
Functional pearl: implicit configurations--or, type classes reflect the values of types
Haskell '04 Proceedings of the 2004 ACM SIGPLAN workshop on Haskell
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS
IEEE Transactions on Computers
Joint cross-layer design for wireless QoS content delivery
EURASIP Journal on Applied Signal Processing
Fast discrete Fourier transform computations using the reduced adder graph technique
EURASIP Journal on Applied Signal Processing
Information Sciences: an International Journal
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pipelined divider with a small lookup table
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection
IEICE - Transactions on Information and Systems
Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1-1, 2n-1)
IEICE - Transactions on Information and Systems
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems
Journal of Signal Processing Systems
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
A generalization of a fast RNS conversion for a new 4-modulus base
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Wireless Communications
Reliable And Secure Chip Level Communication By Residue Number System Code
Journal of Integrated Design & Process Science
Fast modulo 2n+1 multi-operand adders and residue generators
Integration, the VLSI Journal
High-radix residue arithmetic bases for low-power DSP systems
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
A low-complexity high-radix RNS multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Multiple constant multiplication through residue number system
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Digital/analog arithmetic with continuous-valued residues
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Efficient key management FPGA-based cryptosystem using the RNS and iterative coding
International Journal of Information and Communication Technology
Systematic design of full adder-based architectures for convolution
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
Variable word length DSP using serial-by-modulus residue arithmetic
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: digital speech processing - Volume III
Residue arithmetic for designing low-power multiply-add units
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Revisiting sum of residues modular multiplication
Journal of Electrical and Computer Engineering
Hierarchical residue number systems with small moduli and simple converters
International Journal of Applied Mathematics and Computer Science - Semantic Knowledge Engineering
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Efficient clock distribution scheme for VLSI RNS-Enabled controllers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Optimized Implementation of RNS FIR Filters Based on FPGAs
Journal of Signal Processing Systems
Improving modular inversion in RNS using the plus-minus method
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Residue-weighted number conversion using signed-digit number for moduli set {22n - 1, 22n+1 - 1, 2n}
Analog Integrated Circuits and Signal Processing
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