Systematic design of full adder-based architectures for convolution

  • Authors:

  • D. Soudris;V. Paliouras;T. Stouraitis;A. Skavantzos;C. Goutis

  • Affiliations:

  • VLSI Design Lab, Dept. of Electrical Engineering, University of Patras, Greece;VLSI Design Lab, Dept. of Electrical Engineering, University of Patras, Greece;VLSI Design Lab, Dept. of Electrical Engineering, University of Patras, Greece;Dept. of Electrical & Computer Engineering, Louisiana State University;VLSI Design Lab, Dept. of Electrical Engineering, University of Patras, Greece

  • Venue:
  • ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
  • Year:
  • 1993

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Abstract

The systematic design of full adder-based architectures for computing an 1-D circular convolution using the Residue Number System, is introduced. The proposed architectures consist of three stages that exhibit regular and modular structure. Trade offs between hardware complexity and speed are achieved by applying partitioning techniques to each stage. Through a recently-developed multiplierless algorithm, the convolution is reduced to the computation of a series of squaring operations. Based on this fact, a general graph-based methodology for designing circuits that perform raising to the Nth power modulo m is developed.